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IMP5 1 / 1 2 1 15 1
(R)
9-Line SCSI Terminator
ISO 9001 Registered
-35MHz Channel Bandwidth
DESCRIPTION
The IMP5111/5112 SCSI terminators are part of IMP's SCSI terminator family of high-performance, adaptive, non-linear mode SCSI products, which are designed to deliver true UltraSCSI performance in SCSI applications. The low voltage BiCMOS architecture employed in their design offers performance superior to older linear passive and active techniques. IMP's SCSI terminator architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible -- typically 35MHz, which is 100 times faster than the older linear regulator/ terminator approach used by other manufacturers. Products using this older linear regulator approach have bandwidths which are dominated by the output capacitor and which are limited to 500KHz (see further discussion in the Functional Description section). This new architecture also eliminates the output compensation capacitor required in earlier terminator designs. Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond -- providing the highest performance alternative available today. Another key improvement offered by the IMP5111/5112 lies in their ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation is not controlled by the peripheral or host designer and, when problems occur, they are the first to be made aware of the problem. The IMP5111/5112 architecture is much more tolerant of marginal system integrations. Recognizing the needs of portable and configurable peripherals, the IMP5111/5112 have a TTL compatible sleep/disable mode. Quiescent current is typically less than 275A in this mode, while the output capacitance is also less than 3pF. The obvious advantage of extended battery life for portable systems is inherent in the product's sleepmode feature. Additionally, the disable function permits factory-floor or production-line configurability, reducing inventory and product-line diversity costs. Field configurability can also be accomplished without physically removing components which, often times results in field returns due to mishandling. Reduced component count is also inherent in the IMP5111/5112's architecture. Traditional termination techniques require large stabilization and transient protection capacitors of up to 20F in value and size. The IMP5111/5112 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs.
KEY FEATURES
s ULTRA-FAST RESPONSE FOR FAST-20 SCSI APPLICATIONS s 35MHz CHANNEL BANDWIDTH s 3.3V OPERATION s LESS THAN 3pF OUTPUT CAPACITANCE s SLEEP-MODE CURRENT LESS THAN 275A s THERMALLY SELF LIMITING s NO EXTERNAL COMPENSATION CAPACITORS s IMPLEMENTS 8-BIT OR 16-BIT (WIDE) APPLICATIONS s COMPATIBLE WITH ACTIVE NEGATION DRIVERS (60mA / CHANNEL) s COMPATIBLE WITH PASSIVE AND ACTIVE TERMINATIONS s APPROVED FOR USE WITH SCSI 1, 2, 3 AND ULTRA SCSI s HOT SWAP COMPATIBLE s PIN-FOR-PIN COMPATIBLE WITH LX5211 AND UC5606 (IMP5111) s PIN-FOR-PIN COMPATIBLE WITH LX5212 AND UC5603/5613/5614 (IMP5112)
PRODUCT HIGHLIGHT
RE C E I V I N G WAV E F O R M - 20MH Z
D R I V I N G WAV E F O R M - 20MH Z
Receiver 1 Meter, AWG 28 IMP5111/5112 LX5268
Driver IMP 5111/5112 LX5268
PACKAGE ORDER INFORMATION TA (C) 0 to 125
DP Plastic SOIC 16-pin, Power
IMP5111CDP IMP5112CDP
PWP Plastic TSSOP 24-pin, Power
IMP5111CPWP IMP5112CPWP
Note: All surface-mount packages are available in Tape & Reel. Append the letter "T" to part number. (i.e. IMP5111CDPT)
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE PIN OUTS
T7 T8 T9 HEATSINK/GND GND DISCONNECT * T1 T2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
TermPwr Voltage ................................................................................................. +7V Signal Line Voltage .................................................................................... 0V to +7V Regulator Output Current ................................................................................... 0.4A Operating Junction Temperature Plastic (DP, PWP Packages) ......................................................................... 150C Storage Temperature Range .............................................................. -65C to 150C Lead Temperature (Soldering, 10 seconds) ..................................................... 300C
Note 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
T6 T5 N.C. HEATSINK/GND HEATSINK/GND VTERM T4 T3
DP PACKAGE (Top View)
THERMAL DATA
DP PACKAGE:
THERMAL RESISTANCE-JUNCTION TO LEADS, QJL ............................................... 20C/W THERMAL RESISTANCE-JUNCTION TO AMBIENT, QJA ..................... 50C/W
PWP PACKAGE:
THERMAL RESISTANCE-JUNCTION TO LEADS, QJL .............................................. 27C/W THERMAL RESISTANCE-JUNCTION TO AMBIENT, QJA .................. 100C/W
Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow.
T7 T8 T9 N.C. GND HEATSINK/GND HEATSINK/GND HEATSINK/GND HEATSINK/GND DISCONNECT * T1 T2
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
T6 T5 N.C. N.C. HEATSINK/GND HEATSINK/GND HEATSINK/GND HEATSINK/GND N.C. VTERM T4 T3
PWP PACKAGE (Top View)
*DISCONNECT for the IMP5112, and DISCONNECT for the IMP5111.
RECOMMENDED OPERATING CONDITIONS (Note 2) Parameter
Termination Voltage High Level Enable Input Voltage Low Level Disable Input Voltage Operating Virtual Junction Temperature Range IMP5111C/5112C Note 2. Range over which the device is functional.
Symbol
VTERM V IH V IL
Recommended Operating Conditions Min. Typ. Max.
3.3 2 0 0 2 0 5.5 VTERM 0.8 0.8 VTERM 125
Units
V V V V V C
IMP5111 IMP5112 IMP5111 IMP5112
ELECTRICAL CHARACTERISTICS
Term Power = 4.75V unless otherwise specified. Unless otherwise specified, these specifications apply at the recommended operating ambient temperature of TA = 25C. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.
Parameter
Output High Voltage TermPwr Supply Current IMP5111 IMP5112 Output Current DISCONNECT Input Current DISCONNECT Input Current Output Leakage Current IMP5111 IMP5112
Symbol
VOUT ICC
Test Conditions
LX5111/5112 Min. Typ. Max.
2.65 2.85 6 215 275 275 -23 10 -90 -90 10 10 10 3 35 60 9 225
Units
V mA mA A A mA nA A A A nA nA pF MHz mA
IOUT IIN IIN IOL COUT BW ISINK
IMP5111 IMP5112 Capacitance in DISCONNECT Mode ChannelBandwidth Termination Sink Current, per Channel
All data lines = open All data lines = 0.5V DISCONNECT Pin < 0.8V DISCONNECT Pin > 2.0V VOUT = 0.5V DISCONNECT Pin = 4.75V DISCONNECT Pin = 0V DISCONNECT Pin = 0V DISCONNECT Pin = 4.75V DISCONNECT Pin = < 0.8V, VO = 0.5V DISCONNECT Pin = > 2.0V, VO = 0.5V VOUT = 0V, frequency = 1MHz VOUT = 4V
-21
-24
2
BLOCK DIAGRAM
TERM POWER
THERMAL LIMITING CIRCUIT
CURRENT BIASING CIRCUIT
24mA CURRENT LIMITING CIRCUIT
DATA OUTPUT PIN DB(0)
2.85V
DISCONNECT (5111) DISCONNECT (5112)
1.4V 1 OF 9 CHANNELS
FUNCTIONAL DESCRIPTION Cable transmission theory suggests to optimize signal speed and 24mA on assertion, and by imposing 2.85V on deassertion. quality, the termination should act both as an ideal voltage In order to disable the device, the DISCONNECT pin reference when the line is released (deasserted) and as an ideal (DISCONNECT pin for the IMP5112) must be driven logic Low current source when the line is active (asserted). Common active (logic High for the IMP5112). This mode of operation places the terminators, which consist of Linear Regulators in series with devices in a sleep state where a meager 275A of quiescent current resistors (typically 110), are a is consumed. Additionally, all POWER UP / POWER DOWN FUNCTION TABLE compromise. As the line voltage outputs are in a Hi-Z (impedance) increases, the amount of current state. Sleep mode can be used for IMP5111 IMP5112 Quiescent power conservation or to completely decreases linearly by the equation V Outputs DISCONNECT DISCONNECT Current = I * R. The IMP5111/5112, with eliminate the terminator from the their unique new architecture applies SCSI chain. In the second case, H L Enabled 6mA the maximum amount of current termination node capacitance is L H HI Z 275A regardless of line voltage until the important to consider. The terminaOpen Open HI Z 275A termination high threshold (2.85V) tors will appear as a parasitic is reached. distributed capacitance on the line, Acting as a near ideal line terminators, the IMP5111/5112 which can detract from bus performance. For this reason, the closely reproduce the optimum case when the devices are enabled. IMP5111/5112 have been optimized to have only 3pF of To enable the device the DISCONNECT pin (DISCONNECT capacitance per output in the sleep state. pin for the IMP5112) must be pulled logic High (logic Low for An additional feature of the IMP5111/5112 IC's are their the IMP5112). During this mode of operation, quiescent current compatibility with active negation drivers. These devices handle up is 6mA and the devices will respond to line demands by delivering to 60mA of sink current for drivers which exceed the 2.85V output high.
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PACKAGE DIMENSIONS
PWP 24-Pin TSSOP POWER
321
EP
D F AH SEATING PLANE B G L
E
C
M
DIM A B C D E F G H L M P
MILLIMETERS MIN MAX 1.73 1.99 0.25 0.38 0.13 0.22 7.70 7.90 5.20 5.38 0.65 BSC 0.05 0.21 1.63 1.83 0.65 0.95 0 8 7.65 7.90
INCHES MIN MAX 0.068 0.078 0.009 0.015 0.005 0.008 0.303 0.311 0.205 0.212 0.025 BSC 0.002 0.008 0.064 0.072 0.025 0.037 0 8 0.301 0.311
DP
16-Pin Plastic SOIC POWER
16 1
A
9
B
8
P
F
G
D L C M
SEATING PLANE
K
J
DIM A B C D F G J K L M P
MILLIMETERS MIN MAX 9.78 10.01 3.81 4.01 1.35 1.75 0.35 0.46 0.51 0.77 1.27 BSC 0.19 0.25 0.10 0.25 4.82 5.21 0 8 5.79 6.20
INCHES MIN MAX 0.385 0.394 0.150 0.158 0.053 0.069 0.014 0.018 0.020 0.030 0.050 BSC 0.007 0.010 0.004 0.010 0.189 0.205 0 8 0.228 0.244
(R)
ISO 9001 Registered
IMP, Inc. Corporate Headquarters 2830 N. First Street San Jose, CA 95134 Tel: 408.432.9100 Main Tel: 800.438.3722 Fax: 408.434.0335 Fax-on-Demand: 800.249.1614 (USA) Fax-on-Demand: 303.575.6156 (International) e-mail: info@impinc.com http://www.impweb.com
The IMP logo is a registered trademark of IMP, Inc. All other company and product names are trademarks of their respective owners.
(c) 1997 IMP, Inc. Printed in USA Part No.: IMP5111/5112 Document Number: IMP5111-01-9/97
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